1. Field of the Invention
The present invention relates to an electrically erasable nonvolatile semiconductor memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) and a method of rewriting data thereto.
2. Description of the Related Art
A large number of memory elements of an electrically erasable nonvolatile semiconductor memory have been proposed since the early 1980s. The typical ones are EEPROM memory cells each having a floating gate as an electric charge holding layer as described in the following articles.
Article (1): JP-A-61-127179 (based on U.S. patent application Nos. 673946 and 841121) entitled "ELECTRICALLY PROGRAMMED MEMORY UNIT OF A SINGLE TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME", issued to Chang Thomas et al.
Article (2): "DESIGN OF A CMOS SUPER LSI" compiled under the supervision of Takuo Sugano, 1989, pp. 172 to 173.
Article (3): Yasushi Terada "Flash Memory Technology and Its Future", The Institute of Electronics, Information And Communication Engineers, ICD91-134.
Article (4): T. Tanaka et al. "FLASH MEMORY WITH NEGATIVE VOLTAGE SCHEME", The Institute of Electronics, Information And Communication Engineers, ICD91-135.
The EEPROM memory cell employing the floating gate includes, but is not limited to: a crystalline semiconductor silicon substrate of one conductivity type; source and drain diffusion layers which are formed in such a way that the surface of the semiconductor substrate is doped with the impurities of a conductivity type opposite to the conductivity type of the impurities contained in the semiconductor substrate (for example, in the case of a P-type semiconductor substrate doped with boron as the impurities, the source and drain diffusion layers are N-type layers doped with arsenic or phosphorous); a channel region, between the source and drain diffusion layer, through which the minority carriers are to be caused to flow; a thin oxide film provided on the channel region; a floating gate which is made of polycrystalline silicon and is provided on the thin oxide film; and a control gate which is made of polycrystalline silicon and is provided above the floating gate through a thin insulating film.
The principle of the operation of the EEPROM memory cell employing the floating gate is as follows. The electric charges (electrons or positive holes) are injected into the floating gate which is enclosed with the insulating films, thereby to be electrically isolated to be accumulated therein, whereby the threshold voltage of the memory cell is changed and the difference between the threshold voltage before the change and the threshold voltage after the change is utilized as the storage information.
FIGS. 15 and 16 show an example of a structure of the prior art EEPROM memory cell employing the floating gate (this structure is described in the Articles (1) and (2)).
In the structure of this example, one N-channel enhancement MOS transistor (a transistor 20, 21, 22 or 23 in FIG. 15) and one memory cell (a memory cell 24, 25, 26 or 27 in FIG. 15) having a floating gate are required for the data of 1 bit to be stored. Therefore, in the structure shown FIG. 15, the data of 4 bits can be stored.
In FIG. 15, the reference numerals 200 and 201 designate word lines. The word line 200 is connected to a gate of an N-channel enhancement MOS transistor 18 for selecting a byte and gates of the MOS transistors 20 and 21, respectively. On the other hand, the word line 201 is connected to a gate of an N-channel enhancement MOS transistor 19 for selecting a byte and gates of the MOS transistors 22 and 23, respectively.
In FIG. 15, the reference numerals 203 and 204 designate bit lines. The bit line 203 is connected to drains of the MOS transistors 20 and 22, and the bit line 204 is connected to drains of the MOS transistors 21 and 23.
In addition, the reference numeral 202 designates a sense line which is connected to drains of the MOS transistors 18 and 19.
Further, a source of the MOS transistor 18 is connected to a control gate 206 of the memory cells 24 and 25 (the control gate made of polycrystalline silicon is normally formed integrally with the connection line, and so forth on), and a source of the MOS transistor 19 is connected to a control gate 207 of the memory cells 26 and 27.
Further, a source of the MOS transistor 20 and a drain of the memory cell 24, a source of the MOS transistor 21 and a drain of the memory cell 25, a source of the MOS transistor 22 and a drain of the memory cell 26, and a source of the MOS transistor 23 and a drain of the memory cell 27 are formed of common N-type impurity diffusion layers 208, 209, 210 and 211, respectively. Those source and drain are electrically connected to each other.
The reference numeral 205 designates a source line which is connected to sources of the memory cells 24 to 27.
Incidentally, the threshold voltage of each of the MOS transistors 18 to 23 is 1 V for example.
FIG. 16 is a cross sectional view taken along the line B--B of FIG. 15. In the figure, the reference numeral 220 designates a P-type silicon substrate, the reference numerals 205', 208 and 203' designate N-type impurity diffusion layers and the reference numerals 223 and 224 designate a silicon oxide film formed by the thermal oxidation (a gate oxide film). In addition, a part 225 of the silicon thermal oxide film 224 has a thickness which is smaller than those of the remaining part of the silicon thermal oxide film 224 and the silicon thermal oxide film 223 (for example, in the case where the thickness of the remaining part of the silicon thermal oxide film 224 and the silicon thermal oxide film 223 is 50 nm, the thickness of the part 225 is 10 nm).
In addition, the reference numeral 226 designates a floating gate made of polycrystalline silicon for example, the reference numeral 206 designates a control gate made of polycrystalline silicon for example, and the reference numeral 227 designates an insulating film (for example, a thermal oxide film having a thickness of about 25 nm) between the floating gate 226 and the control gate 206.
Further, the reference numeral 200 designates a gate (formed integrally with the word line 200 of FIG. 15) of the MOS transistor 20 which is made of polycrystalline silicon for example, the reference numeral 228 designates an insulating layer, and the reference numeral 203 designates a bit line which is made of aluminium as the main material. In addition, the reference numeral 229 designates a contact hole through which the bit line 203 is connected to an N-type impurity diffusion layer 203' constituting the drain of the MOS transistor 20. Incidentally, the floating gate 226 is entirely enclosed within the periphery thereof by the insulating films and is electrically isolated from other conductive parts.
FIG. 17 is a circuit diagram showing an electrical equivalent circuit of each of the memory cells shown in FIGS. 15 and 16. In the figure, the reference numeral 206 designates the control gate to which a voltage Vg is to be applied, the reference numeral 208 designates the drain to which a voltage Vd is to be applied, the reference numeral 205' designates the source to which a voltage Vs is to be applied, and the reference numeral 220 designates the semiconductor substrate to which a voltage Vsub is to be applied. The insulating films 224 and 227 of FIG. 16 can be expressed in the form of electrical capacitors, respectively. Then, it is assumed that Cip is representative of a capacitance between the floating gate 226 and the control gate 206, Cd a capacitance between the floating gate 226 and the drain 208, Cs a capacitance between the floating gate 226 and the source 205' and Csub a capacitance between the floating gate 226 and the semiconductor substrate 220. Then, if an electrical potential at the floating gate 226 is assumed to be Vf, the following expression is established on the basis of the principle of charge conservation. ##EQU1##
When the relationship of Vs=Vsub=Vd=0 V is established in the expression (1), the following expression is obtained. EQU Vf=Vg.multidot.Rp EQU where Rp=Cip/(Cip+Cd+Csub+Cs) (2)
Rp is called "the coupling ratio" and is generally in the range of 0.55 to 0.7.
Next, the description will hereinbelow be given with respect to the operation of the rewriting and reading of the data to and from EEPROM having the above-mentioned structure.
In FIG. 15, in the case where the data is written to the memory cell 24, for example, the electric potentials on the word line 200, the sense line 202 and the bit line 203 are respectively made 20 V, 0 V and 20 V, and the source line 205 is opened, whereby the MOS transistors 18, 20 and 21 are turned on, and the electric potential at the control gate becomes 0 V and the electric potential at the drain 208 of the memory cell 24 becomes about 18 V (the voltage value which is obtained by subtracting the threshold voltage of the MOS transistor 20 from 20 V (including the substrate effect)). As a result, the voltage of about 7 V is induced in the floating gate of the memory cell 24 (refer to FIG. 16). At this time, since the part 225 of the silicon thermal oxide film 224 shown in FIG. 16 has the thickness of 10 nm, due to the difference in electric potential between the floating gate 226 and the drain 208, the Fowler-Nordheim tunnel current (the tunnel current conforming to the Fowler-Nordheim expression (hereinafter, referred to as "the F-N tunnel current" for short, when applicable)) is caused to flow through the part 225. This F-N tunnel current is, in general, caused to flow when an electric field, which is equal to or higher than 10 MV/cm, is applied to a very thin oxide film (having a thickness equal to or smaller than 10 nm). Then, by flowing of the F-N tunnel current, the positive holes are injected from the drain 208 into the floating gate 226 so that the threshold voltage of the memory cell 24 is lowered (for example, if the initial threshold voltage of the memory cell 24 is 2 V, the threshold voltage after the writing operation will be lowered to -2 to -3 V). At this time, the voltages on the word lines other than the word line 200 and the bit lines other than the bit line 203, that is in the figure, the voltages on the word line 201 and the bit line 204 are made 0 V, whereby a high voltage is not applied to the memory cells other than the memory cell 24. As a result, the writing of the data is now performed.
In the case where the data stored in the memory cell 24 is erased, for example, 20 V is applied to the word line 200, 20 V to the sense line 202 and 0 V to the bit line 203, then the voltage at the control gate 206 becomes about 18 V and the voltage at the drain 208 becomes 0 V. As a result, the voltage of about 11 V is induced in the floating gate 226 of the memory cell 24, and the F-N tunnel current is caused to flow through the part 225, and thus the electrons are injected into the floating gate 226, so that the threshold voltage of the memory cell 24 is elevated (for example in the range of 6 to 7 V). At this time, the voltage applied to the word lines other than the word line 200, e.g., the word line 201 is made 0 V, whereby the control gate 207 is enabled and thus the data stored in the memory cells 26 and 27 is not erased. But, in this case, since 0 V is applied to all the bit lines, the data stored in all the memory cells connected to the same node as that of the control gate 206, for example, the memory cell 25, are erased.
In the case where the data stored in the memory cell 24 is read out, for example, 5 V, 3 V and 2 V are respectively applied to the word line 200, the sense line 202 and the bit line 203, whereby the MOS transistors 18 and 20 are turned on, the voltage at the drain 208 of the memory cell 24 goes to 2 V, and the voltage at the control gate 206 goes to 5 V. At this time, in the case where the threshold voltage of the memory cell 24 is higher, that is, in the range of 6 to 7 V, this memory cell 24 is in the off state and thus no current flows between the drain and the source. On the other hand, in the case where the threshold voltage of the memory cell 24 is lower, that is, in the range of -2 to -3 V, this memory cell 24 is in the on state and thus the current is caused to flow between the drain and the source. The existence (or the magnitude) of the current is detected, whereby the reading of the data stored in the memory cell is performed.
FIGS. 18 and 19 show another example of a structure of the prior art EEPROM employing the floating gate (this structure is described in the Articles (1), (3) and (4)).
In FIG. 18, the reference numerals 30, 31, 32 and 33 designate memory cells, the reference numerals 300 and 301 designate word lines, and the reference numerals 302 and 303 designate bit lines. Then, the word line 300 is connected to the control gate of the memory cells 30 and 31, and the word line 301 is connected to the control gate of the memory cells 32 and 33. In addition, the bit line 302 is connected to the drains of the memory cells 30 and 32, and the bit line 303 is connected to the drains of the memory cells 31 and 33. Further, the reference numeral 304 designates a source line which is connected to the sources of the memory cells 30 to 33.
FIG. 19 shows a cross sectional view taken along the line C--C of FIG. 18. In the figure, the reference numeral 305 designates a P-type silicon substrate, the reference numerals 302' and 304' designate N-type impurity diffusion layers, and the reference numeral 306 designates a thin silicon thermal oxide film (having a thickness of 10 nm for example) (the gate oxide film). In addition, the reference numeral 309 designates a floating gate which is made of polycrystalline silicon for example, the reference numeral 300 designates a control gate which is made, for example, of polycrystalline silicon (formed integrally with the word line 300 of FIG. 18), and the reference numeral 307 designates an insulating film (an insulating film which has a thickness of 25 nm and is made up of an oxide film and a nitride film) provided between the floating gate 309 and the control gate 300. Further, the reference numeral 310 designates an insulating layer, and the reference numeral 302 designates a bit line which is made of aluminium as the main material. Moreover, the reference numeral 308 designates a contact hole through which the bit line 302 is connected to the N-type impurity diffusion layer 302'.
Next, the description will hereinbelow be given with respect to the rewriting and the reading of the data to and from EEPROM having the above-mentioned structure.
Now, it is assumed that under the condition in which no electric charge is injected into the floating gate of each memory cell, the threshold voltage of each of the memory cells is 2 V, for example.
In the case where the data is written to the memory cell 30, the electric potentials on the word line 300, the word line 301, the bit line 302, the bit line 303 and the source line 304 are respectively made 12 V, 0 V, 5 V, 0 V and 0 V. At this time, if the coupling ratio Rp of the memory cells is assumed to be 0.6 V, the voltage of about 7 V is induced in the floating gate 309 of FIG. 19. As a result, a channel layer of electrons is formed between the drain 302' and the source 304' of the memory cell. In addition, due to the high gate voltage and the high drain voltage, the hot electrons are generated in the high electric field region in the vicinity of the drain 302' and then the hot electrons thus generated surmount a potential barrier between the silicon and the gate oxide film to be injected into the floating gate 309. This phenomenon is called "the channel hot electron injection" (hereinafter, referred to as "the CHE injection" for short, when applicable). As a result of generation of this CHE injection, the threshold voltage of the memory cell 30 of FIG. 18 is elevated up to 6 to 8 V for example so that the writing operation is performed. At this time, prior to the generation of the CHE injection, a current of 30 .mu.A to 1 mA is caused to flow through the portion between the drain and the source of the memory cell 30. Further, since both the word line 301 and the bit line 303 are at 0 V, no data is written to the memory cells 31 to 33.
In the case where the data stored in the memory cell 30 is erased, for example, the electric potential on the word line 300 is made -9 V, the electric potential on the word line 301 is made 0 V, both the bit lines 302 and 303 are released, and the electric potential on the source line 304 is made 5 V. As a result, the voltage of about -7 V is induced in the floating gate of the memory cell 30, and thus the electrons are extracted in the form of the F-N tunnel current from the floating gate 309 into the source 304' via the gate oxide film 306. Then, the quantity of extracted electrons is suitably adjusted by a control circuit, whereby the threshold voltage of the memory cell 30 is lowered to 2 to 3 V. Incidentally, in this example as well, all the memory cells which have the control gate common to the memory cell 30 through the word line 300, for example, the memory cell 31 is erased with the data stored therein. Since the word line 301 is at 0 V, the data stored in the memory cells 32 and 33 is not erased.
In the case where the data stored in the memory cell 30 is read out, for example, the electric potentials on the word line 300, the word line 301, the bit line 302, the bit line 303, and the source line 304 are respectively made 5 V, 0 V, 1 V, 0 V and 0 V. In this connection, when the threshold voltage of the memory cell 30 is high (for example, in the range of 6 to 8 V), no current is caused to flow through the portion between the drain and the source of the memory cell 30. However, when the threshold voltage of the memory cell 30 is low (for example, in the range of 2 to 3 V), a current is caused to flow through the portion between the drain and the source of the memory cell 30.
In the first prior art shown in FIGS. 15 and 16, the writing of the data to the memory cell is performed by the injection of the electric charges utilizing the F-N tunnel current. Therefore, there is provided the advantage that in the writing operation, only the relative small current (for example, a current of 10 to 1000 pA per memory cell) is required for the memory cell.
However, in the first prior art, since the writing of the data is performed selectively among the cell array, the separating transistors, such as the MOS transistors 20 to 23 of FIG. 15, are required for separating the memory cells from one another. That is, in the case where those separating MOS transistors 20 to 23 are not provided, if the data is written to the memory cell 24 for example by the above-mentioned method, at the same time, the same data will also be written to all the memory cells connected to the bit line 203, for example, the memory cell 26. Thus, if one separating transistor is provided for 1 bit, as the area occupied by such separating transistors, the area of about 80 to 150 .mu.m.sup.2 for example will be required. Therefore, there arises the problem that the promotion of the large scale integration of the cell array is hindered.
On the other hand, in the second prior art shown in FIGS. 18 and 19, there is provided the advantage that the separating transistor as in the first prior art is not required. On the other hand, since the CHE injection from the vicinity of the drain is utilized during the writing operation, there is provided the disadvantage that the large current needs to be caused to flow through the corresponding part of the memory cell. That is, in the case of the writing operation utilizing the F-N tunnel current, the quantity of necessary current is small. Therefore, even when the semiconductor memory is operated by using the power source voltage of 3 V for example, the booster circuit such as a charge pump circuit is provided in the integrated circuit, whereby the semiconductor memory can be operated by using the single power source voltage. On the other hand, in the case where the writing of the data is performed by utilizing the CHE injection from the vicinity of the drain, there is a limit to the reduction of the drain voltage because the hot electrons need to be generated in the corresponding part. That is, although the drain voltage of 6 to 7 V is required for the integrated circuit having a minimum processing size at a 0.8 .mu.m level for example, even if the minimum processing size is reduced to 0.5 .mu.m level, the drain voltage can be lowered to no more than 5 V. Therefore, it is substantially impossible to operate the semi-conductor memory by using the reduced single power source voltage.
In addition, even if the drain voltage in the writing operation utilizing the CHE injection from the vicinity of the drain can be lowered to about 3 V, in this case, there arises the problem that the malwriting of the data due to the drain voltage in the reading operation occurs easier. That is, in the case where the writing of the data is performed by utilizing the CHE injection from the vicinity of the drain, if the difference between the drain voltage in the writing operation and that in the reading operation is small, the problem of the malwriting easily occurs due to the drain voltage in the reading operation so that the reliability of the memory is degraded.
Thus, in the case of the prior art writing method utilizing the CHE injection from the vicinity of the drain, there arises the problem that it is difficult to promote the reduction of the power source voltage, as compared with the writing method utilizing the F-N tunnel current.